形式等效性检查
形式等效性检查[1]（英語：formal equivalence checking）是电子设计自动化的一个步骤，通常是在集成电路设计中，通过一些数学方法（如二元决策图、布尔可满足性问题），来对不同电路之间进行形式验证，比较它们在行为上是否等效。
参考文献
- Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field. This article was derived, with permission, from Volume 2, Chapter 4, Equivalence Checking, by Fabio Somenzi and Andreas Kuehlmann.
- R.E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers., C-35, pp. 677–691, 1986. The original reference on BDDs.